“Penn State leads semiconductor packaging, heterogeneous integration center”

[BobPSU92]

See the link below. From the article:

”UNIVERSITY PARK, Pa. — The Semiconductor Research Corporation (SRC)’s Joint University Microelectronics Program 2.0 (JUMP 2.0), a consortium of industrial partners in cooperation with the Defense Advanced Research Projects Agency (DARPA), has announced the creation of a $32.7 million, Penn State-led Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES).

Madhavan Swaminathan, head of electrical engineering and William E. Leonhard Endowed Chair in Penn State College of Engineering’s School of Electrical Engineering and Computer Science, will direct the center. CHIMES is one of seven centers funded through the JUMP 2.0 initiative for improving the performance, efficiency, and capabilities of electronic systems for emerging commercial and defense applications.

“The global semiconductor industry is projected to become a trillion-dollar industry by 2030 — driven primarily by computing, data storage, wireless and automotive applications — which is incredible considering that it took 55 years to reach half a trillion dollars in size and will take less than 10 years to double,” Swaminathan said. “Such phenomenal growth requires new and transformative logic, memory and interconnect technologies to overcome the inevitable slowdown of traditional dimensional scaling of semiconductors.”

This is the focus of CHIMES, according to Swaminathan. Fourteen university partners — including Georgia Tech; Columbia University; Cornell University; Arizona State University; George Washington University; Massachusetts Institute of Technology; Rice University; Stanford University; University of California, Davis; University of California, Los Angeles; University of California, San Diego; University of Colorado; and University of Illinois, Chicago — will collaborate to advance heterogenous integration, the efficient and effective integration and packaging of semiconductor devices, chips and other components.”

https://www.psu.edu/news/engineering/story/penn-state-leads-semiconductor-packaging-heterogeneous-integration-center/

Why bother? I don’t see how this will help Franklin.

 

[step.eng69]

See the link below. From the article:

”UNIVERSITY PARK, Pa. — The Semiconductor Research Corporation (SRC)’s Joint University Microelectronics Program 2.0 (JUMP 2.0), a consortium of industrial partners in cooperation with the Defense Advanced Research Projects Agency (DARPA), has announced the creation of a $32.7 million, Penn State-led Center for Heterogeneous Integration of Micro Electronic Systems (CHIMES).

Madhavan Swaminathan, head of electrical engineering and William E. Leonhard Endowed Chair in Penn State College of Engineering’s School of Electrical Engineering and Computer Science, will direct the center. CHIMES is one of seven centers funded through the JUMP 2.0 initiative for improving the performance, efficiency, and capabilities of electronic systems for emerging commercial and defense applications.

“The global semiconductor industry is projected to become a trillion-dollar industry by 2030 — driven primarily by computing, data storage, wireless and automotive applications — which is incredible considering that it took 55 years to reach half a trillion dollars in size and will take less than 10 years to double,” Swaminathan said. “Such phenomenal growth requires new and transformative logic, memory and interconnect technologies to overcome the inevitable slowdown of traditional dimensional scaling of semiconductors.”

This is the focus of CHIMES, according to Swaminathan. Fourteen university partners — including Georgia Tech; Columbia University; Cornell University; Arizona State University; George Washington University; Massachusetts Institute of Technology; Rice University; Stanford University; University of California, Davis; University of California, Los Angeles; University of California, San Diego; University of Colorado; and University of Illinois, Chicago — will collaborate to advance heterogenous integration, the efficient and effective integration and packaging of semiconductor devices, chips and other components.”

https://www.psu.edu/news/engineering/story/penn-state-leads-semiconductor-packaging-heterogeneous-integration-center/

Why bother? I don’t see how this will help Franklin.

Obviously.

 

[Woodpecker]

“Such phenomenal growth requires new and transformative logic, memory and interconnect technologies to overcome the inevitable slowdown of traditional dimensional scaling of semiconductors.”

I'm so dumb that I didn't know that dimensional scaling of semiconductors had become a tradition.

 

[BobPSU92]

I'm so dumb that I didn't know that dimensional scaling of semiconductors had become a tradition.

It‘s especially big at Christmas.

 

[Leo Ridens]

I'm so dumb that I didn't know that dimensional scaling of semiconductors had become a tradition.

You want to shrink the size of a transistor (specifically the distance between the source and drain, the two contacts that conduct the electrical current between them) in order to get higher device speed (the smaller the distance the electrons have to travel, the faster the device). To do that, you also shrink the thickness of the gate oxide (the insulator that turns the transistor on and off). You also shrink the thickness of the conducting silicon layer that forms the conducting channel. That is dimensional scaling. The problem is that below a certain thickness of the silicon conducting channel, silicon loses its ability to conduct electricity (because of quantum mechanical effects - don't ask). Silicon technology is rapidly approaching this "silocon roadblock", a brick wall of device sizr and hence device speed). There are ways around this, but they are not easy. People are looking at semiconductors other than silicon, but the tech industry will have to retool everything to switch from silicon technology because they have 60 years of experience with it, and the new materials technologies are in their infancy,

 

[BobPSU92]

You want to shrink the size of a transistor (specifically the distance between the source and drain, the two contacts that conduct the electrical current between them) in order to get higher device speed (the smaller the distance the electrons have to travel, the faster the device). To do that, you also shrink the thickness of the gate oxide (the insulator that turns the transistor on and off). You also shrink the thickness of the conducting silicon layer that forms the conducting channel. That is dimensional scaling. The problem is that below a certain thickness of the silicon conducting channel, silicon loses its ability to conduct electricity (because of quantum mechanical effects - don't ask). Silicon technology is rapidly approaching this "silocon roadblock", a brick wall of device sizr and hence device speed). There are ways around this, but they are not easy. People are looking at semiconductors other than silicon, but the tech industry will have to retool everything to switch from silicon technology because they have 60 years of experience with it, and the new materials technologies are in their infancy,

Stop making stuff up.

 

[ApexLion]

You want to shrink the size of a transistor (specifically the distance between the source and drain, the two contacts that conduct the electrical current between them) in order to get higher device speed (the smaller the distance the electrons have to travel, the faster the device). To do that, you also shrink the thickness of the gate oxide (the insulator that turns the transistor on and off). You also shrink the thickness of the conducting silicon layer that forms the conducting channel. That is dimensional scaling. The problem is that below a certain thickness of the silicon conducting channel, silicon loses its ability to conduct electricity (because of quantum mechanical effects - don't ask). Silicon technology is rapidly approaching this "silocon roadblock", a brick wall of device sizr and hence device speed). There are ways around this, but they are not easy. People are looking at semiconductors other than silicon, but the tech industry will have to retool everything to switch from silicon technology because they have 60 years of experience with it, and the new materials technologies are in their infancy,

Finally somethin' in your wheelhouse on this board Leo. It was a long wait.

Appreciate your explanation. thank you

 

[Leo Ridens]

Stop making stuff up.

Would you believe me if I said that the same scaling rules apply to scones and tongs?

 

[BobPSU92]

Would you believe me if I said that the same scaling rules apply to scones and tongs?

Now you’re talking!

 

[Leo Ridens]

Finally somethin' in your wheelhouse on this board Leo. It was a long wait.

Appreciate your explanation. thank you

Thanks. I have loved and followed PSU football since I enrolled as a grad student at University Park in the 70s, but having the build of a stereotypical physicist and thus having never played the sport at any level, I am not an expert in the Xs and Os.

 

[Woodpecker]

You want to shrink the size of a transistor (specifically the distance between the source and drain, the two contacts that conduct the electrical current between them) in order to get higher device speed (the smaller the distance the electrons have to travel, the faster the device). To do that, you also shrink the thickness of the gate oxide (the insulator that turns the transistor on and off). You also shrink the thickness of the conducting silicon layer that forms the conducting channel. That is dimensional scaling. The problem is that below a certain thickness of the silicon conducting channel, silicon loses its ability to conduct electricity (because of quantum mechanical effects - don't ask). Silicon technology is rapidly approaching this "silocon roadblock", a brick wall of device sizr and hence device speed). There are ways around this, but they are not easy. People are looking at semiconductors other than silicon, but the tech industry will have to retool everything to switch from silicon technology because they have 60 years of experience with it, and the new materials technologies are in their infancy,

How fast do electrons travel that these distances that are reduced have a significant effect on device speed? I always thought that they were whipping around pretty fast so that a reduction of a few microns, even millions of such reductions, wouldn't make much difference in 10^15 floating point operations per second. Obviously I'm wrong which is why we biologists aren't tasked with staying on top of these sorts of things.

 

[Leo Ridens]

How fast do electrons travel that these distances that are reduced have a significant effect on device speed? I always thought that they were whipping around pretty fast so that a reduction of a few microns, even millions of such reductions, wouldn't make much difference in 10^15 floating point operations per second. Obviously I'm wrong which is why we biologists aren't tasked with staying on top of these sorts of things.

At the risk of someone replying with “Take it to the Science-Math Nerd Board” (Tom, that’s an idea for a new board. LionJim, Are you with me on that?), here is a simplified answer to your question. The maximum speed of electrons in silicon is about 6.5 x10E7 cm/sec, which is called the saturation velocity. That is a misnomer in that a velocity is a vector with a specific direction and its magnitude is the speed, but it is understood that the direction is along the applied voltage difference. When you apply a voltage between two contacts (the source and drain in a transistor), the electrons quickly accelerate to the saturation velocity. As an analogy, when you floor the pedal of your Lamborghini, it takes a bit of time to reach its maximum speed (Full disclosure: I drive a 2014 Honda CRV hand-me-down from my wife). Similarly, it takes a bit of time for the electrons to reach saturation velocity, so let’s assume that in a properly designed silicon transistor the electrons travel at 5 x10E7 cm/sec.

Since distance = speed x time, so for a transistor with a source-drain separation of 5 micrometers (5x10E-6 meters = 5x10E-4 cm, which is the size of a transistor from the mid-1960s) the transit time is

time = distance/speed = 5x10E-4 cm / 5 x10E7 cm/sec = 10E-11 sec.

Frequency = 1/time so this corresponds to a frequency of 1 /10E-11 sec = 10E11 sec -1 = 100 GigaHz where a Hz = 1/sec.

Similarly, we will soon be making circuits with transistors having source-drain separations of 5 nanometers = 5 x 10E-7 cm, which would give an operating frequency of 10,000 GHz. However, the transistors of the mid 1960s had operating frequencies nowhere near 100 GHz and the new ones coming on line soon will have frequencies nowhere 10,000 GHz. What is going on?

A transistor operates by applying a voltage to a metal gate on top of the gate oxide. This forms a capacitor, which takes time to charge (turn on the transistor) and a roughly equal time to turn it off. The charging/discharging time depends on the capacitance of the gate, which is much slower than the frequencies you might expect from the saturation velocity of the electrons calculated above. To reduce the capacitance, you make the gate as small as possible, which is why (among other reasos) you also scale the gate size as you shrink the source-drain separation.

Now it gets even worse when you hook a bunch of transistors together to form a circuit. They have to talk to each other via thin metal connectors, which also have capacitance. Hook a few billion together to form a chip where the transistors have to talk to each other and the chip speed is even slower. Chip design is extremely complex, and I have greatly simpified the complxities of real chip circuits. I am glad that I am not a chip designer.

Now Tom, how about that new Science-Math Nerd Board?

Also, for the football-only readers who got this far, when will Harbaugh find an NFL team willing to take him?